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1 ? caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003, 2005. all rights reserved. all other trademarks mentioned are the property of their respective owners. july 11, 2005 82c54 cmos programmable intervel timer the intersil 82c54 is a high performance cmos programmable interval timer manufactured using an advanced 2 micron cmos process. the 82c54 has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 8mhz (82c54) or 10mhz (82c54-10) or 12mhz (82c54-12). the high speed and industry standard configuration of the 82c54 make it compatible with the intersil 80c86, 80c88, and 80c286 cmos microprocessors along with many other industry standard proces sors. six programmable timer modes allow the 82c54 to be used as an event counter, elapsed time indicator, programmable one-shot, and many other applications. static cmos circuit design insures low power operation. the intersil advanced cmos pr ocess results in a significant reduction in power with performance equal to or greater than existing equivalent products. features 8mhz to 12mhz clock input frequency compatible with nmos 8254 - enhanced version of nmos 8253 three independent 16-bit counters six programmable counter modes status read back command binary or bcd counting fully ttl compatible single 5v power supply low power - iccsb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 a - iccop . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma at 8mhz operating temperature ranges - cx82c54 . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c - ix82c54 . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c - md82c54 . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c pb-free plus anneal available (rohs compliant) pinouts 82c54 (pdip, cerdip) top view 82c54 (plcc/clcc) top view 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 d7 d6 d5 d4 d3 d2 d1 d0 clk 0 out 0 gate 0 gnd vcc rd cs a1 a0 out 2 clk 1 gate 1 out 1 wr clk 2 gate 2 gnd nc out 1 gate 1 clk 1 out 0 gate 0 d7 nc vcc wr rd d5 d6 cs a1 a0 clk2 nc gate 2 out 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 d3 d2 d1 d0 d4 nc clk 0 data sheet fn2970.4
2 82c54 ordering information part numbers temperature range package pkg. dwg. # 8mhz 10mhz 12mhz cp82c54 cp82c54-10 cp82c54-12 0 o c to +70 o c 24 lead pdip e24.6 cp82c54z (see note) cp82c54-10z (see note) cp82c54-12z (see note) 0 o c to +70 o c 24 lead pdip** (pb-free) e24.6 cs82c54* cs82c54-10* cs82c54-12 0 o c to +70 o c 28 lead plcc n28.45 cs82c54z* (see note) cs82c54-10z* (see note) cs82c54-12z* (see note) 0 o c to +70 o c 28 lead plcc (pb-free) n28.45 id82c54 - - -40 o c to +85 o c 24 lead cerdip f24.6 ip82c54 ip82c54-10 - -40 o c to +85 o c 24 lead pdip e24.6 ip82c54z (see note) ip82c54-10z (see note) - -40 o c to +85 o c 24 lead pdip** (pb-free) e24.6 is82c54* is82c54-10* - -40 o c to +85 o c 28 lead plcc n28.45 is82c54z (see note) is82c54-10z (see note) - -40 o c to +85 o c 28 lead plcc (pb-free) n28.45 md82c54/b - - -55 o c to +125 o c 24 lead cerdip f24.6 smd # 8406501ja - - -55 o c to +125 o c 24 lead cerdip f24.6 smd# 84065013a - 84065023a -55 o c to +125 o c 28 lead clcc j28.a contact factory fo r availability. *add ?96? suffix for tape and reel. **pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder proces sing applications. note: intersil pb-free plus anneal products em ploy special pb-free material sets; mold ing compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020.
3 82c54 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . . gnd-0.5v to v cc +0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range. . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range cx82c54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c ix82c54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c md82c54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c thermal resistance (typical) ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 55 12 clcc package. . . . . . . . . . . . . . . . . . . 65 14 pdip package*. . . . . . . . . . . . . . . . . . . 55 n/a plcc package. . . . . . . . . . . . . . . . . . . 60 n/a storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c maximum junction temperature ceramic package. . . . . . . .+175 o c maximum junction temperature plastic package . . . . . . . . .+150 o c maximum lead temperature package (soldering 10s). . . . .+300 o c (plcc - lead tips only) *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2250 gates caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. dc electrical specifications v cc = +5.0v 10%, includes all temperature ranges symbol parameter min max units test conditions vih logical one input voltage 2.0 - v cx82c54, ix82c54 2.2 - v md82c54 vil logical zero input voltage - 0.8 v - voh output high voltage 3.0 - v ioh = -2.5ma v cc -0.4 - v ioh = -100 a vol output low voltage - 0.4 v iol = +2.5ma ii input leakage current -1 +1 a vin = gnd or v cc dip pins 9,11,14-16,18-23 io output leakage current -10 +10 a vout = gnd or v cc dip pins 1-8 iccsb standby power supply current - 10 av cc = 5.5v, vin = gnd or v cc , outputs open, counters programmed iccop operating power supply current - 10 ma v cc = 5.5v, clk0 = clk1 = clk2 = 8mhz, vin = gnd or v cc , outputs open capacitance t a = +25 o c; all measurements referenced to device gnd, note 1 symbol parameter typ units test conditions cin input capacitance 20 pf freq = 1mhz cout output capacitance 20 pf freq = 1mhz ci/o i/o capacitance 20 pf freq = 1mhz note: 1. not tested, but characterized at initial design and at major process/design changes.
4 82c54 ac electrical specifications v cc = +5.0v 10%, includes all temperature ranges symbol parameter 82c54 82c54-10 82c54-12 units test conditions min max min max min max read cycle (1) tar address stable before rd 30 - 25 - 25 - ns 1 (2) tsr cs stable before rd 0-0-0-ns 1 (3) tra address hold time after rd 0-0-0-ns 1 (4) trr rd pulse width 150 - 95 - 95 - ns 1 (5) trd data delay from rd - 120 - 85 - 85 ns 1 (6) tad data delay from address - 210 - 185 - 185 ns 1 (7) tdf rd to data floating 5 85 5 65 5 65 ns 2, note 1 (8) trv command recovery time 200 - 165 - 165 - ns write cycle (9) taw address stable before wr 0-0-0-ns (10) tsw cs stable before wr 0-0-0-ns (11) twa address hold time after wr 0-0-0-ns (12) tww wr pulse width 95 - 95 - 95 - ns (13) tdw data setup time before wr 140 - 95 - 95 - ns (14) twd data hold time after wr 25-0-0-ns (15) trv command recovery time 200 - 165 - 165 - ns clock and gate (16) tclk clock period 125 dc 100 dc 80 dc ns 1 (17) tpwh high pulse width 60 - 30 - 30 - ns 1 (18) tpwl low pulse width 60 - 40 - 30 - ns 1 (19) tr clock rise time - 25 - 25 - 25 ns (20) tf clock fall time - 25 - 25 - 25 ns (21) tgw gate width high 50 - 50 - 50 - ns 1 (22) tgl gate width low 50 - 50 - 50 - ns 1 (23) tgs gate setup time to clk 50 - 40 - 40 - ns 1 (24) tgh gate hold time after clk 50 - 50 - 50 - ns 1 (25) tod output delay from clk - 150 - 100 - 100 ns 1 (26) todg output delay from gate - 120 - 100 - 100 ns 1 (27) two out delay from mode write - 260 - 240 - 240 ns 1 (28) twc clk delay for loading 0 55 0 55 0 55 ns 1 (29) twg gate delay for sampling -5 40 -5 40 -5 40 ns 1 (30) tcl clk setup for count latch -40 40 -40 40 -40 40 ns 1 note: 1. not tested, but characterized at initial design and at major process/design changes.
5 82c54 functional diagram control word register read/ write logic data/ bus buffer counter 2 counter 1 counter 0 internal bus internal bus control logic control word register status latch status register clk n gate n out n out 2 gate 2 clk 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 wr rd d 7 - d 0 a 0 a 1 cs ol m ol l ce cr m cr l counter internal block diagram 8 pin description symbol dip pin number type definition d7 - d0 1 - 8 i/o data: bi-directional three-stat e data bus lines, connected to system data bus. clk 0 9 i clock 0: clock input of counter 0. out 0 10 o out 0: output of counter 0. gate 0 11 i gate 0: gate input of counter 0. gnd 12 ground: power supply connection. out 1 13 o out 1: output of counter 1. gate 1 14 i gate 1: gate input of counter 1. clk 1 15 i clock 1: clock input of counter 1. gate 2 16 i gate 2: gate input of counter 2. out 2 17 o out 2: output of counter 2. clk 2 18 i clock 2: clock input of counter 2. a0, a1 19 - 20 i address: select inputs for one of the three counters or control word register for read/write operations. normally connected to the system address bus. cs 21 i chip select: a low on this input enables the 82c54 to respond to rd and wr signals. rd and wr are ignored otherwise. rd 22 i read: this input is lo w during cpu read operations. wr 23 i write: this input is low during cpu write operations. v cc 24 - v cc : the +5v power supply pin. a 0.1 f capacitor between pins vcc and gnd is recommended for decoupling. a1 a0 selects 0 0 counter 0 0 1 counter 1 1 0 counter 2 1 1 control word register
6 82c54 functional description general the 82c54 is a programmable interval timer/counter designed for use with microcomputer systems. it is a general purpose, multi-timing element that can be treated as an array of i/o ports in the system software. the 82c54 solves one of the most common problems in any microcomputer system, the gene ration of accurate time delays under software control. instead of setting up timing loops in software, the programmer configures the 82c54 to match his requirements and programs one of the counters for the desired delay. after the desired delay, the 82c54 will interrupt the cpu. software overhead is minimal and variable length delays can easily be accommodated. some of the other computer/timer functions common to microcomputers which can be implemented with the 82c54 are: real time clock event counter digital one-shot programmable rate generator square wave generator binary rate multiplier complex waveform generator complex motor controller data bus buffer this three-state, bi-directional, 8-bit buffer is used to interface the 82c54 to the system bus (see figure 1). read/write logic the read/write logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 82c54. a1 and a0 select one of the three counters or the control word register to be read from/written into. a ?low? on the rd input tells the 82c54 that the cpu is reading one of the counters. a ?low? on the wr input tells the 82c54 that the cpu is writing either a control word or an initial count. both rd and wr are qualified by cs ; rd and wr are ignored unless the 82c54 has been selected by holding cs low. control word register the control word register (figure 2) is selected by the read/write logic when a1, a0 = 11. if the cpu then does a write operation to the 82c54, the data is stored in the control word register and is interpreted as a control word used to define the counter operation. the control word register can only be written to; status information is available with the read-back command. counter 0, counter 1, counter 2 these three functional blocks ar e identical in operation, so only a single counter will be described. the internal block diagram of a signal counter is shown in figure 3. the counters are fully independent. each counter may operate in a different mode. the control word register is sh own in the figure; it is not part of the counter itself, but its contents determine how the counter operates. control word register counter 2 counter 1 counter 0 internal bus out 2 gate 2 clk 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 wr rd d 7 - d 0 a 0 a 1 cs figure 1. data bus buffer and read/write logic functions 8 data/ bus buffer read/ write logic read/ write logic data/ bus buffer internal bus out 2 gate 2 clk 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 wr rd d 7 - d 0 a 0 a 1 cs figure 2. control word register and counter functions 8 control word register counter 2 counter 1 counter 0
7 82c54 the status register, shown in the figure, when latched, contains the current contents of the control word register and status of the output and null count flag. (see detailed explanation of the read-back command.) the actual counter is labeled ce (for counting element). it is a 16-bit presettable synchronous down counter. olm and oll are two 8-bit latches. ol stands for ?output latch?; the subscripts m and l for ?most significant byte? and ?least significant byte?, respecti vely. both are normally referred to as one unit and called just ol. these latches normally ?follow? the ce, but if a suitable counter latch command is sent to the 82c54, the latches ?latch? the present count until read by the cpu and then return to ?following? the ce. one latch at a time is enabled by the counter?s control logic to drive the internal bus. this is how the 16-bit counter communicates over the 8-bit internal bus. note that the ce itself cannot be read; whenever you read the count, it is the ol that is being read. similarly, there are two 8-bit registers called crm and crl (for ?count register?). both are normally referr ed to as one unit and called just cr. when a new count is written to the counter, the count is stored in the cr and later transferred to the ce. the control logic allows one register at a time to be loaded from the internal bus. both byte s are transferred to the ce simultaneously. crm and crl are cleared when the counter is programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero. note that the ce cannot be written into; whenever a count is written, it is written into the cr. the control logic is also shown in the diagram. clk n, gate n, and out n are all connected to the outside world through the control logic. 82c54 system interface the 82c54 is treated by the system software as an array of peripheral i/o ports; three are counters and the fourth is a control register for mode programming. basically, the select inputs a0 , a1 connect to the a0, a1 address bus signals of the cpu. the cs can be derived directly from the address bus using a linear select method or it can be connected to t he output of a decoder. operational description general after power-up, the state of the 82c54 is undefined. the mode, count value, and output of all counters are undefined. how each counter operates is determined when it is programmed. each counter must be programmed before it can be used. unused counters need not be programmed. programming the 82c54 counters are programmed by writing a control word and then an initial count. all control words are written into the control word register, which is selected when a1, a0 = 11. the control word specifies which counter is being programmed. by contrast, initial counts are written into the counters, not the control word register. the a1, a0 inputs are used to select the counter to be written into. the format of the initial count is determined by the control word used. write operations the programming procedure for the 82c54 is very flexible. only two conventions need to be remembered: 1. for each counter, the control word must be written before the initial count is written. 2. the initial count must follow th e count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). internal bus control logic control word register status latch status register clk n gate n out n ol m ol l ce cr m cr l figure 3. counter internal block diagram address bus (16) control bus data bus (8) i/or i/ow wr rd cs a0 a1 a1 a0 8 counter 0 outgate clk counter 1 counter 2 out gate clk out gate clk d0 - d7 82c54 figure 4. counter internal block diagram
8 82c54 since the control word register and the three counters have separate addresses (selected by the a1, a0 inputs), and each control word specifies the counter it applies to (sc0, sc1 bits), no special instruction sequence is required. any programming sequence that follo ws the conventions above is acceptable. control word format a1, a0 = 11; cs = 0; rd = 1; wr = 0 d7 d6 d5 d4 d3 d2 d1 d0 sc1 sc0 rw1 rw0 m2 m1 m0 bcd sc - select counter sc1 sc0 0 0 select counter 0 0 1 select counter 1 1 0 select counter 2 1 1 read-back command (see read operations) rw - read/write rw1 rw0 0 0 counter latch command (see read operations) 0 1 read/write least si gnificant byte only. 1 0 read/write most significant byte only. 1 1 read/write least signif icant byte first, then most significant byte. m - mode m2 m1 m0 0 0 0 mode 0 0 0 1 mode 1 x 1 0 mode 2 x 1 1 mode 3 1 0 0 mode 4 1 0 1 mode 5 bcd - binary coded decimal 0 binary counter 16-bit 1 binary coded decimal (bcd) counter (4 decades) note: don?t care bits (x) should be 0 to insure compatibility with future products. possible programming sequence a1 a0 control word - counter 0 1 1 lsb of count - counter 0 0 0 msb of count - counter 0 0 0 control word - counter 1 1 1 lsb of count - counter 1 0 1 msb of count - counter 1 0 1 control word - counter 2 1 1 lsb of count - counter 2 1 0 msb of count - counter 2 1 0 possible programming sequence a1 a0 control word - counter 0 1 1 control word - counter 1 1 1 control word - counter 2 1 1 lsb of count - counter 2 1 0 lsb of count - counter 1 0 1 lsb of count - counter 0 0 0 msb of count - counter 0 0 0 msb of count - counter 1 0 1 msb of count - counter 2 1 0 possible programming sequence a1 a0 control word - counter 2 1 1 control word - counter 1 1 1 control word - counter 0 1 1 lsb of count - counter 2 1 0 msb of count - counter 2 1 0 lsb of count - counter 1 0 1 msb of count - counter 1 0 1 lsb of count - counter 0 0 0 msb of count - counter 0 0 0
9 82c54 a new initial count may be written to a counter at any time without affecting the counter?s programmed mode in any way. counting will be affected as described in the mode definitions. the new count must follow the programmed count format. if a counter is programmed to read/write two-byte counts, the following precaution applies. a program must not transfer control between writing the firs t and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. read operations it is often desirable to read the value of a counter without disturbing the count in progress . this is easily done in the 82c54. there are three possible methods for reading the counters. the first is through the read-back command, which is explained later. the second is a simple read operation of the counter, which is selected with the a1, a0 inputs. the only requirement is that the clk input of the selected counter must be inhibited by using either the gate input or external logic. otherwise, the count may be in process of changing when it is read, giving an undefined result. counter latch command the other method for reading the counters involves a special software command called the ?counter latch command?. like a control word, this command is written to the control word register, which is selected when a1, a0 = 11. also, like a control word, the sc0, sc1 bits select one of the three counters, but two other bits, d5 and d4, distinguish this command from a control word. . the selected counter?s output latch (ol) latches the count when the counter latch command is received. this count is held in the latch until it is read by the cpu (or until the counter is reprogrammed). the count is then unlatched automatically and the ol returns to ?following? the counting element (ce). this allows reading the contents of the counters ?on the fly? without affecting counting in progress. multiple counter latch commands may be used to latch more than one counter. each latched counter?s ol holds its count until read. counter latch commands do not affect the programmed mode of the counter in any way. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the first counter latch command was issued. with either method, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other; read or write or programming operations of other counters may be inserted between them. another feature of the 82c54 is that reads and writes of the same counter may be interleaved; for example, if the counter is programmed for two byte counts, the following sequence is valid. 1. read least significant byte. 2. write new least significant byte. 3. read most significant byte. 4. write new most significant byte. if a counter is programmed to read or write two-byte counts, the following precaution applies: a program must not transfer control between reading the first and second byte to another routine which also reads from that same counter. otherwise, an incorrect count will be read. read-back command the read-back command allows the user to check the count value, programmed mode, and current state of the out pin and null count flag of the selected counter(s). the command is written into the control word register and has the format shown in figure 5. the command applies to possible programming sequence a1 a0 control word - counter 1 1 1 control word - counter 0 1 1 lsb of count - counter 1 0 1 control word - counter 2 1 1 lsb of count - counter 0 0 0 msb of count - counter 1 0 1 lsb of count - counter 2 1 0 msb of count - counter 0 0 0 msb of count - counter 2 1 0 note: in all four examples, all counters are programmed to read/write two-byte counts. these are only four of many programming sequences. a1, a0 = 11; cs = 0; rd = 1; wr = 0 d7 d6 d5 d4 d3 d2 d1 d0 sc1sc00 0xxxx sc1, sc0 - specify counter to be latched sc1 sc0 counter 00 0 01 1 10 2 1 1 read-back command d5, d4 - 00 designates counter latch command, x - don?t care. note: don?t care bits (x) should be 0 to insu re compatibility with future products.
10 82c54 the counters selected by setting their corresponding bits d3, d2, d1 = 1. the read-back command may be used to latch multiple counter output latches (ol) by setting the count bit d5 = 0 and selecting the desired counter(s). this signal command is functionally equivalent to several counter latch commands, one for each counter latched. each counter?s latched count is held until it is read (or th e counter is reprogrammed). that counter is automatically unlatched when read, but other counters remain latched until they are read. if multiple count read-back commands are issued to the same counter without reading the count, all bu t the first are ignored; i.e., the count which will be read is t he count at the time the first read-back command was issued. the read-back command may also be used to latch status information of selected counter(s) by setting status bit d4 = 0. status must be latched to be read; status of a counter is accessed by a read from that counter. the counter status format is shown in figure 6. bits d5 through d0 contain the counte r?s programmed mode exactly as written in the last mode control word. output bit d7 contains the current state of the out pin. this allows the user to monitor the counter?s output via software, possibly eliminating some hardware from a system. null count bit d6 indicates when the last count written to the counter register (cr) ha s been loaded into the counting element (ce). the exact time this happens depends on the mode of the counter and is desc ribed in the mode definitions, but until the counter is loaded in to the counting element (ce), it can?t be read from the counter. if the count is latched or read before this time, the count value will not reflect the new count just written. the operation of null count is shown below. this action: causes: a. write to the control word register:(1) . . . . null count = 1 b. write to the count register (cr):(2) . . . . . null count = 1 c. new count is loaded into ce (cr - ce) . . null count = 0 1. only the counter specified by the control word will have its null count set to 1. null count bits of other counters are unaffected. 2. if the counter is programmed for two-byte counts (least significant byte then most significant byte) null count goes to 1 when the second byte is written. if multiple status latch operations of the counter(s) are performed without reading the status, all but the first are ignored; i.e., the status that wi ll be read is the status of the counter at the time the first status read-back command was issued. both count and status of t he selected counter(s) may be latched simultaneously by setting both count and status bits d5, d4 = 0. this is functionally the same as issuing two separate read-back commands at once, and the above discussions apply here also. specifically, if multiple count and/or status read-back commands are issued to the same counter(s) without any intervening reads, all but the first are ignored. this is illustrated in figure 7. if both count and status of a counter are latched, the first read operation of that counter will return latched status, regardless of which was latched first. the next one or two reads (depending on whether the counter is programmed for one or two type counts) return latched count. subsequent reads return unlatched count. a0, a1 = 11; cs = 0; rd = 1; wr = 0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 count status cnt 2cnt 1cnt 0 0 d5:0=latch count of selected counter (s) d4:0=latch status of selected counter(s) d3:1=select counter 2 d2:1=select counter 1 d1:1=select counter 0 d0:reserved for future expansion; must be 0 figure 5. read-back command format d7 d6 d5 d4 d3 d2 d1 d0 output null count rw1 rw0 m2 m1 m0 bcd d7:1=out pin is 1 0=out pin is 0 d6:1=null count 0=count available for reading d5-d0=counter programmed mode (see control word formats) figure 6. status byte
11 82c54 mode definitions the following are defined for use in describing the operation of the 82c54. clk pulse - a rising edge, then a falling edge, in that order, of a counter?s clk input. trigger - a rising edge of a counter?s gate input. counter loading - the transfer of a count from the cr to the ce (see ?functional description?) mode 0: interrupt on terminal count mode 0 is typically used for event counting. after the control word is written, out is initially low, and will remain low until the counter reaches zero. out then goes high and remains high until a new count or a new mode 0 control word is written to the counter. gate = 1 enables counting; gate = 0 disables counting. gate has no effect on out. after the control word and initial count are written to a counter, the initial count will be loaded on the next clk pulse. this clk pulse does not decrement the count, so for an initial count of n, out does not go high until n + 1 clk pulses after the initial count is written. if a new count is written to the counter it will be loaded on the next clk pulse and counting will continue from the new count. if a two-byte count is written, the following happens: 1. writing the first byte disables counting. out is set low immediately (no clock pulse required). 2. writing the second byte allows the new count to be loaded on the next clk pulse. this allows the counting sequence to be synchronized by software. again out does not go high until n + 1 clk pulses after the new count of n is written. commands description result d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 0 0 0 1 0 read-back count and status of counter 0 count and status latched for counter 0 1 1 1 0 0 1 0 0 read-back status of counter 1 status latched for counter 1 1 1 1 0 1 1 0 0 read-back status of counters 2, 1 status latched for counter 2, but not counter 1 1 1 0 1 1 0 0 0 read-back count of counter 2 count latched for counter 2 1 1 0 0 0 1 0 0 read-back count and status of counter 1 count latched for counter 1, but not status 1 1 1 0 0 0 1 0 read-back status of counter 1 command ignored, status already latched for counter 1 figure 7. read-back command example cs rd wr a1 a0 01000write into counter 0 01001write into counter 1 01010write into counter 2 01011write control word 00100read from c ounter 0 00101read from c ounter 1 00110read from c ounter 2 00111no-operation (three-state) 1xxxxno-operation (three-state) 0 1 1 x x no-operation (three-state) figure 8. read/write operations summary
12 82c54 if an initial count is written while gate = 0, it will still be loaded on the next clk pulse. when gate goes high, out will go high n clk pulses later; no clk pulse is needed to load the counter as this has already been done. notes: the following conventions apply to all mode timing diagrams. 1. counters are programmed for binary (not bcd) counting and for reading/writing least signifi cant byte (lsb) only. 2. the counter is always selected (cs always low). 3. cw stands for ?control word?; cw = 10 means a control word of 10, hex is written to the counter. 4. lsb stands for least significant ?byte? of count. 5. numbers below diagrams are count values. the lower number is the least significant byte. the upper number is the most significant byte. since the count er is programmed to read/write lsb only, the most significant byte cannot be read. 6. n stands for an undefined count. 7. vertical lines show tran sitions between count values. mode 1: hardware retriggerable one-shot out will be initially high. out will go low on the clk pulse following a trigger to begin the one-shot pulse, and will remain low until the counter reaches zero. out will then go high and remain high until the clk pulse after the next trigger. after writing the control word and initial count, the counter is armed. a trigger results in loading the counter and setting out low on the next clk pulse, thus starting the one-shot pulse n clk cycles in duration. the one-shot is retriggerable, hence out will remain low for n clk pulses after any trigger. the one-shot pulse can be repeated without rewriting the same count into the counter. gate has no effect on out. if a new count is written to the counter during a one-shot pulse, the current one-shot is not affected unless the counter is retriggerable. in that case, the counter is loaded with the new count and the one-shot pulse continues until the new count expires. cw = 10 lsb = 4 wr clk gate out wr clk gate out wr clk gate out cw = 10 lsb = 3 cw = 10 lsb = 3 lsb = 2 nnnn 0 4 0 3 0 2 0 1 0 0 ff ff ff fe nnnn 0 3 0 2 0 2 0 2 0 1 0 0 ff ff nnnn 0 3 0 2 0 1 0 2 0 1 0 0 ff ff figure 9. mode 0 wr clk gate out wr clk gate out wr clk gate out nnnn 0 3 0 2 0 1 0 0 ff ff 0 3 0 2 n cw = 12 lsb = 3 cw = 12 lsb = 3 cw = 12 lsb = 2 lsb = 4 nnnn 0 2 0 1 0 0 ff ff ff fe 0 4 0 3 n nnnn 0 3 0 2 0 1 0 3 0 2 0 1 0 0 n figure 10. mode 1
13 82c54 mode 2: rate generator this mode functions like a divide-by-n counter. it is typically used to generate a real time clock interrupt. out will initially be high. when the initial count has decremented to 1, out goes low for one clk pulse. out then goes high again, the counter reloads the initial count and the process is repeated. mode 2 is periodic; the same sequence is repeated indefinitely. for an initial count of n, the sequence repeats every n clk cycles. gate = 1 enables counting; gate = 0 disables counting. if gate goes low during an output pulse, out is set high immediately. a trigger reloads the counter with the initial count on the next clk pulse; out goes low n clk pulses after the trigger. thus the gate input can be used to synchronize the counter. after writing a control word and initial count, the counter will be loaded on the next clk pulse. out goes low n clk pulses after the initial count is written. this allows the counter to be synchronized by software also. writing a new count while counti ng does not affect the current counting sequence. if a trigger is received after writing a new count but before the end of the current period, the counter will be loaded with the new count on the next clk pulse and counting will continue from the end of the current counting cycle. mode 3: square wave mode mode 3 is typically used for b aud rate generation. mode 3 is similar to mode 2 except for the duty cycle of out. out will initially be high. when half the initial count has expired, out goes low for the remainder of the count. mode 3 is periodic; the sequence above is repeated i ndefinitely. an initial count of n results in a square wave with a period of n clk cycles. gate = 1 enables counting; gate = 0 disables counting. if gate goes low while out is low, out is set high immediately; no clk pulse is required. a trigger reloads the counter with the initial count on the next clk pulse. thus the gate input can be used to synchronize the counter. after writing a control word and initial count, the counter will be loaded on the next clk pulse. this allows the counter to be synchronized by software also. writing a new count while counting does not affect the current counting sequence. if a trigger is received after writing a new count but before the end of the current half- cycle of the square wave, the c ounter will be lo aded with the new count on the next clk pulse and counting will continue from the new count. otherwise, the new count will be loaded at the end of the current half-cycle. nnnn 0 2 0 1 0 3 0 2 0 1 0 3 0 3 nnnn 0 2 0 2 0 3 0 2 0 1 0 3 0 3 nnnn 0 3 0 2 0 1 0 5 0 4 0 3 0 4 wr clk gate out cw = 14 lsb = 3 wr clk gate out cw = 14 lsb = 3 wr clk gate out cw = 14 lsb = 4 lsb = 5 figure 11. mode 2 nnn n 0 2 0 4 0 2 0 4 0 2 0 4 0 2 0 4 0 4 0 2 nnn n 0 4 0 2 0 5 0 2 0 5 0 4 0 2 0 5 0 5 0 2 nnn n 0 2 0 4 0 2 0 2 0 2 0 4 0 2 0 4 0 4 0 2 wr clk gate out cw = 16 lsb = 4 wr clk gate out wr clk gate out cw = 16 lsb = 5 cw = 16 lsb = 4 figure 12. mode 3
14 82c54 mode 3 is implemented as follows even counts - out is initially high. the initial count is loaded on one clk pulse and then is decremented by two on succeeding clk pulses. when the count expires, out changes value and the counter is reloaded with the initial count. the above process is repeated indefinitely. odd counts - out is initially high. t he initial count is loaded on one clk pulse, decremented by one on the next clk pulse, and then decremented by two on succeeding clk pulses. when the count expires, out goes low and the counter is reloaded with the initial count. the count is decremented by three on the next clk pulse, and then by two on succeeding clk pulses. when the count expires, out goes high again and the counter is reloaded with the initial count. the above process is repeated indefinitely. so for odd counts, out will be high for (n + 1)/2 counts and low for (n - 1)/2 counts. mode 4: software triggered mode out will be initially high. when the initial count expires, out will go low for one clk pulse then go high again. the counting sequence is ?triggered? by writing the initial count. gate = 1 enables counting; gate = 0 disables counting. gate has no effect on out. after writing a control word and initial count, the counter will be loaded on the next clk pulse. this clk pulse does not decrement the count, so for an initial count of n, out does not strobe low until n + 1 clk pulses after the initial count is written. if a new count is written during counting, it will be loaded on the next clk pulse and counting will continue from the new count. if a two-byte count is written, the following happens: 1. writing the first byte has no effect on counting. 2. writing the second byte allows the new count to be loaded on the next clk pulse. this allows the sequence to be ?retriggered? by software. out strobes low n + 1 clk pulses after the new count of n is written. mode 5: hardware triggered strobe (retriggerable) out will initially be high. counting is triggered by a rising edge of gate. when the initial count has expired, out will go low for one clk pulse and then go high again. after writing the control word and initial count, the counter will not be loaded until the clk pulse after a trigger. this clk pulse does not decrement the count, so for an initial count of n, out does not strobe low until n + 1 clk pulses after trigger. a trigger results in the counter being loaded with the initial count on the next clk pulse. the counting sequence is triggerable. out will not strobe low for n + 1 clk pulses after any trigger gate has no effect on out. if a new count is written during counting, the current counting sequence will not be affected. if a trigger occurs after the new count is written but before the current count expires, the nnnn 0 2 0 1 0 0 ff ff ff fe ff fd 0 3 wr clk gate out cw = 18 lsb = 3 wr clk gate out wr clk gate out cw = 18 lsb = 3 cw = 18 lsb = 3 nnn 0 3 0 2 0 1 0 2 0 1 0 0 ff ff nn n n 0 3 0 3 0 2 0 1 0 0 ff ff 0 3 lsb = 2 n figure 13. mode 4
15 counter will be loaded with new count on the next clk pulse and counting will continue from there. operation common to all modes programming when a control word is written to a counter, all control logic, is immediately reset and out goes to a known initial state; no clk pulses are required for this. gate the gate input is always sampled on the rising edge of clk. in modes 0, 2, 3 and 4 the gate input is level sensitive, and logic level is sampled on the rising edge of clk. in modes 1, 2, 3 and 5 the gate input is rising-edge sensitive. in these modes, a rising edge of gate (trigger) sets an edge-sensitive flip-flop in the counter. this flip-flop is then sampled on the next rising edge of clk. the flip-flop is reset immediately after it is sampled. in this way, a trigger will be detected no matter when it occurs - a high logic level does not have to be maintained until the next rising edge of clk. note that in modes 2 a nd 3, the gate input is both edge-and level-sensitive. counter new counts are loaded and counters are decremented on the falling edge of clk. the largest possible initial count is 0; this is equivalent to 2 16 for binary counting and 10 4 for bcd counting. the counter does not stop when it reaches zero. in modes 0, 1, 4, and 5 the counter ?wraps around? to the highest count, either ffff hex for binary counting or 9999 for bcd counting, and continues counting. modes 2 and 3 are periodic; the counter reloads it self with the initial count and continues counting from there. nnnn 0 3 0 2 0 1 0 0 ff ff 0 3 wr clk gate out cw = 1a lsb = 3 nnnn 0 3 0 2 0 3 0 2 0 1 nnnn 0 3 0 2 0 1 0 0 ff ff ff fe wr clk gate out cw = 1a lsb = 3 wr clk gate out cw = 1a lsb = 3 n nn 0 0 ff ff lsb = 5 n 0 5 0 4 figure 14. mode 5 signal status modes low or going low rising high 0 disables counting - enables counting 1 - 1) initiates counting 2) resets output after next clock - 2 1) disables counting 2) sets output immediately high initiates counting enables counting 3 1) disables counting 2) sets output immediately high initiates counting enables counting 4 1) disables counting - enables counting 5 - initiates counting - figure 15. gate pin operations summary mode min count max count 010 110 220 320 410 510 note: 0 is equivalent to 2 16 for binary counting and 10 4 for bcd counting. figure 16. minimum and maximum initial counts 82c54
16 timing waveforms figure 17. write figure 18. read figure 19. recovery a0 - a1 cs data bus wr (12) tww (13) tdw (10) tsw (9) taw valid twd (14) twa (11) valid a0 - a1 cs rd data bus (2) tsr (6) tad (5) trd (4) trr (7) tdf tra (3) tar (1) (8) (15) trv rd , wr 82c54
17 burn-in circuits md82c54 (cerdip) mr82c54 (clcc) notes: 1. v cc = 5.5v 0.5v 2. gnd = 0v 3. vih = 4.5v 10% 4. vil = -0.2v to 0.4v 5. r1 = 47k ? 5% 6. r2 = 1.0k ? 5% 7. r3 = 2.7k ? 5% 8. r4 = 1.8k ? 5% 9. r5 = 1.2k ? 5% 10. c1 = 0.01 f min 11. f0 = 100khz 10% 12. f1 = f0/2, f2 = f1/2, ...f12 = f11/2 figure 20. clock and gate timing waveforms (continued) wr clk gate out mode count (see note) (17) tpwh (18) tpwl (16) tclk tgs (21) tgw (27) two tgs (23) tgh (24) tgl todg (26) tf (20) tod (25) tgh (24) note: last byte of count being written (19) tr (22) (23) tcl (30) twc (28) r1 r1 r1 r1 r1 r1 r1 r1 r2 r1 r1 r1 r1 r1 r2 r1 r1 r2 r1 vcc gnd q5 q4 a f1 q7 a q3 f2 q8 q2 vcc gnd f9 f11 f0 a q6 gnd q1 f10 f12 v cc a 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 v cc c1 r4 r3 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 vcc/2 q6 gnd open vcc/2 f1 q7 r1 r1 r1 r1 r2 r5 gnd q5 q4 q8 open f2 vcc/2 r1 r1 r1 r1 r1 r2 f9 f10 f11 open gnd f12 f0 r5 r1 r5 r1 r2 r1 r1 r1 r1 r1 vcc q2 q1 open c1 q3 vcc vcc 82c54
18 die characteristics die dimensions: 129mils x 155mils x 19mils (3270 m x 3940 m x 483 m) metallization: type: si-al-cu thickness: metal 1: 8k? 0.75k? metal 2: 12k? 1.0k? glassivation: ty p e : n i t r ox thickness: 10k? 3.0k? metallization mask layout 82c54 cs a1 a0 clk2 out2 gate2 d4 d3 d2 d1 d0 clk0 d5 d6 d7 vcc wr rd out0 gate0 gnd out1 gate1 clk1 82c54
19 82c54 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in ca se of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not in clude dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e24.6 (jedec ms-011-aa issue b) 24 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.150 1.290 29.3 32.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n24 249 rev. 0 12/93
20 82c54 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. c onverted millimeter dimensions are not necessarily exact. 2. dimensions and toleranc ing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0 .25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l n28.45 (jedec ms-018ab issue a) 28 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.485 0.495 12.32 12.57 - d1 0.450 0.456 11.43 11.58 3 d2 0.191 0.219 4.86 5.56 4, 5 e 0.485 0.495 12.32 12.57 - e1 0.450 0.456 11.43 11.58 3 e2 0.191 0.219 4.86 5.56 4, 5 n28 286 rev. 2 11/97
21 82c54 ceramic leadless chip carrier packages (clcc) d j x 45 o d3 b h x 45 o a a1 e l l3 e b3 l1 d2 d1 e 1 e2 e1 l2 plane 2 plane 1 e3 b2 0.010 e h s s 0.010 e f s s -e- 0.007 e f m s hs b1 -h- -f- j28.a mil-std-1835 cqcc1-n28 (c-4) 28 pad ceramic leadless chip carrier package symbol inches millimeters notes min max min max a 0.060 0.100 1.52 2.54 6, 7 a1 0.050 0.088 1.27 2.23 - b----- b1 0.022 0.028 0.56 0.71 2, 4 b2 0.072 ref 1.83 ref - b3 0.006 0.022 0.15 0.56 - d 0.442 0.460 11.23 11.68 - d1 0.300 bsc 7.62 bsc - d2 0.150 bsc 3.81 bsc - d3 - 0.460 - 11.68 2 e 0.442 0.460 11.23 11.68 - e1 0.300 bsc 7.62 bsc - e2 0.150 bsc 3.81 bsc - e3 - 0.460 - 11.68 2 e 0.050 bsc 1.27 bsc - e1 0.015 - 0.38 - 2 h 0.040 ref 1.02 ref 5 j 0.020 ref 0.51 ref 5 l 0.045 0.055 1.14 1.40 - l1 0.045 0.055 1.14 1.40 - l2 0.075 0.095 1.90 2.41 - l3 0.003 0.015 0.08 0.038 - nd 7 7 3 ne 7 7 3 n28 283 rev. 0 5/18/94 notes: 1. metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the opti onal plane 2 terminals. 2. unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. symbol ?n? is the maximum number of terminals. symbols ?nd? and ?ne? are the number of terminals along the sides of length ?d? and ?e?, respectively. 4. the required plane 1 terminals and optional plane 2 terminals (if used) shall be elec trically connected. 5. the corner shape (square, notch, radius, etc.) may vary at the manufacturer?s option, from that shown on the drawing. 6. chip carriers shall be constructed of a minimum of two ceramic layers. 7. dimension ?a? controls the over all package thickness. the maxi- mum ?a? dimension is package hei ght before being solder dipped. 8. dimensioning and tolerancing per ansi y14.5m-1982. 9. controlling dimension: inch.
22 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com 82c54 ceramic dual-in-line frit seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f24.6 mil-std-1835 gdip1-t24 (d-3, configuration a) 24 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.290 - 32.77 5 e 0.500 0.610 12.70 15.49 5 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.120 0.200 3.05 5.08 - q 0.015 0.075 0.38 1.91 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n24 248 rev. 0 4/94
82c54 printer friendly version cmos programmable interval timer datasheets, related docs & simulations description key features parametric data related devices ordering information part no. design-in status temp. package msl price us $ 84065013a active mil 28 ld clcc n/a 93.67 8406501ja active mil 24 ld cerdip n/a 53.89 84065023a active mil 28 ld clcc n/a 159.96 cp82c54 active comm 24 ld pdip n/a 3.07 cp82c54-10 active comm 24 ld pdip n/a 3.73 cp82c54-10z active comm 24 ld pdip n/a 3.73 cp82c54-12 active comm 24 ld pdip n/a 5.71 cp82c54-12z active comm 24 ld pdip n/a 5.71 cp82c54z active comm 24 ld pdip n/a 3.07 cs82c54 active comm 28 ld plcc 3 3.47 cs82c54-10 active comm 28 ld plcc 3 4.13 cs82c54-1096 active comm 28 ld plcc t+r 3 4.20 cs82c54-10z active comm 28 ld plcc 3 4.13 cs82c54-10z96 active comm 28 ld plcc t+r 3 4.20 cs82c54-12 active comm 28 ld plcc 3 7.01 cs82c54-12z active comm 28 ld plcc 3 7.01 CS82C54-12Z96 active comm 28 ld plcc t+r 3 7.01 cs82c5496 active comm 28 ld plcc t+r 3 3.53 cs82c54z active comm 28 ld plcc 3 3.47 cs82c54z96 active comm 28 ld plcc t+r 3 3.53 id82c54 active ind 24 ld cerdip n/a 13.28 ip82c54 active ind 24 ld pdip n/a 7.39 ip82c54-10 active ind 24 ld pdip n/a 8.48 ip82c54-10z active ind 24 ld pdip n/a 8.48 ip82c54z active ind 24 ld pdip n/a 7.39 is82c54 active ind 28 ld plcc 3 8.15 is82c54-10 active ind 28 ld plcc 3 10.19 is82c54-1096 active ind 28 ld plcc t+r 3 10.29 is82c54-10z active ind 28 ld plcc 3 10.19 is82c54-10z96 active ind 28 ld plcc t+r 3 10.29 is82c5496 active ind 28 ld plcc t+r 3 8.25 is82c54z active ind 28 ld plcc 3 8.15
md82c54/b active mil 24 ld cerdip n/a 56.12 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the intersil 82c54 is a high performance cmos programmable interval timer manufactured using an advanced 2 micron cmos process. the 82c54 has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 8mhz (82c54) or 10mhz (82c54-10) or 12mhz (82c54- 12). the high speed and industry standard configuration of the 82c54 make it compatible with the intersil 80c86, 80c88, and 80c286 cmos microprocessors along with many other industry standard processors. six programmable timer modes allow the 82c54 to be used as an event counter, elapsed time indicator, programmable one-shot, and many other applications. static cmos circuit design insures low power operation. the intersil advanced cmos process results in a significant reduction in power with performance equal to or greater than existing equivalent products. key f eatures 8mhz to 12mhz clock input frequency compatible with nmos 8254 enhanced version of nmos 8253 three independent 16-bit counters six programmable counter modes status read back command binary or bcd counting fully ttl compatible single 5v power supply low power iccsb 10a iccop 10ma at 8mhz operating temperature ranges cx82c54 0c to +70c ix82c54 -40c to +85c md82c54 -55c to +125c pb-free plus anneal available (rohs compliant) related documentation datasheet(s): cmos programmable interval timer military smd(s): radiation hardened cmos programmable interval timer technical homepage: digital ics military/space ics parametric data features ? 8mhz to 12mhz clock input frequency ? compatible with nmos 8254 - enhanced version of nmos 8253 related devices parametric table
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